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SOC
/ ASIC Design Turnkey Service |
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Technology:
65nm, 90nm, 0.13um, 0.18um, 0.25um, 0.35um, 0.5um |
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SOC
Implementation Platform Service: |
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Spec-in,
Project-in, RTL to CHIP, Netlist to CHIP, RTL QA, STA, Signal Integrity,
LAYOUT, Low Power Design, DFT,
ATPG, BSD, Mem_BIST, Power Analysis(RTL, Netlist, Package) |
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SiP
Design Turnkey Service |
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Platform
ASIC Design Turnkey Service |
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ARM-based Platform；Gate Array Platform；Structured ASIC Platform |
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IP(Special
I/O, Mixed Signal, High Density Memory...) Design Service: |
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Special
I/O, ADC & DAC, High Density Memory；Customized, Modify, Athoring |
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GATE
ARRAY(Mask/Metal Type FPGA) Design Turnkey Service |
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FPGA To ASIC(ASIC To ASIC) Design Turnkey Sercivce |
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Structured
ASIC IP(Platform ASIC) Design Turnkey Service |
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LAYOUT(APR,
Full custom, Shrinking) Design Service |
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COT(GDSII
TO CHIP) Turnkey Service |
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MPW
(Multi-Project Wafer) Shuttle Bus Service |
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SOC
/ ASIC Product Turnkey Service(PGC + TSMC + ASE): |
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Testing
Program Development(Agilent 93000, HILEVEL, Credence Sapphire D-10), Logistic,
WIP, Tape-out, Package, Testing, Yield Improvement, Corner Run, Failure
Analysis, Reliability, Wafer Allocation |
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