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SOC / ASIC Design Turnkey Service |
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SOC Implementation Platform Service: |
| Spec-in, Project-in, RTL to CHIP, Netlist to CHIP, RTL QA, STA, Signal Integrity, LAYOUT, Low Power Design, DFT, ATPG, BSD, Mem_BIST, Power Analysis(RTL, Netlist, Package) | |
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SIP Design Turnkey Service |
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IP(Special I/O, Mixed Signal, High Density Memory...) Design Service: |
| Customized, Modify, Athoring, Shrink, Decrease Mask Layer | |
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GATE ARRAY(Mask/Metal Type FPGA) Design Turnkey Service |
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Structured ASIC IP(Platform ASIC) Design Turnkey Service |
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LAYOUT(APR, Full custom, Shrinking) Design Service |
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COT(GDSII TO CHIP) Turnkey Service |
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MPW (Multi-Project Wafer) Shuttle Bus Service |
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SOC / ASIC Product Turnkey Service(PGC + TSMC + ASE): |
| Testing Program Development(Agilent 93000, HILEVEL), Logistic, WIP, Tape-out, Package, Testing, Yield Improvement, Corner Run, Failure Analysis, Reliability, Wafer Allocation | |
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