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Device	Total I/O Pads	Max I/O	Total Gate	DLM Usable Gate	TLM Usable Gate	Remark
HDA9068 HDA9080 HDA9100 HDA9120 HDA9144 HDA9160 HDA9184 HDA9208 HDA9240 HDA9256 HDA9280	84 96 116 136 160 176 200 224 256 272 296	68 80 100 120 144 160 184 208 240 256 280	11078 16100 26640 39820 59094 73950 99528 128898 174110 199014 239760	4985 7245 11988 15231 22603 28285 38069 49303 66596 76122 91708	8308 12075 19980 25385 37672 47143 63449 82172 110995 126871 152847	Available Available Available Available Available

Engineer Sample lead time: 3 ~ 4 weeks

Mass Production lead time: 4 ~ 5 weeks

SUPER HOT RUN lead time: 2 ~ 3 weeks

Provide Gate Array Design Kit and Library

Above Estimated Schedule is based on 1P2M

Normal lead time: 2 ~ 3 days / layer

Technology Feature:

Metal memory compiler (single-port RAM, dual-port RAM and ROM).
Provide embedded ARRAY, embedded memory, embedded custom blocks, embedded IP, embedded special I/O……etc.
If customers request other devices(body), PGC can provide customize body devices for customers.(HIGH PIN COUNT BODY DEVICES)
Pad size: 　75 x 663.9um² (width x length)
Pad opening: 　86 x 86um² (width x length)

Note:

Usable gates are estimated; the actual number of usable gates is design dependent.
I/O pads can be used as VDD/VSS pads.
There are four (4) dedicated VDD/VSS pads for each corner cell in the chip.

HIGH PIN COUNT BODY DEVICES

Device	1P2M Usable Gates (1)	1P3M Usable Gates (1)	Total I/O Pads	Max I/O
HDA9324 HDA9392 HDA9460 HDA9532 HDA9660 HDA9664 HDA9728 HDA9792	146428 216644 300366 404096 516209 634007 765288 907402	244046 361073 500610 673493 860348 1056679 1275480 1512336	340 408 476 548 616 680 744 808	324 392 460 532 600 664 728 792

Note: Usable gates are estimated; the actual number of usable gates is design dependent.