Untitled Document

Device	1P2M Usable Gates	1P3M Usable 　Gates	Total I/O Pads	Max I/O
HDA8048 HDA8068 HDA8080 HDA8100 HDA8120 HDA8144 HDA8160 HDA8184 HDA8208 HDA8240 HDA8256	1318 3229 4762 7938 10246 15301 19225 25962 33770 45590 52126	2196 5382 7938 13230 17077 25501 32043 43270 56284 75984 86877	64 84 96 116 136 160 176 200 224 256 272	48 68 80 100 120 144 160 184 208 240 256

Engineer Sample lead time: 3 ~ 4 weeks

Mass Production lead time: 4 ~ 5 weeks

SUPER HOT RUN lead time: 2 ~ 3 weeks

Provide Gate Array Design Kit and Library

Above Estimated Schedule is based on 1P2M

Normal lead time: 2 ~ 3 days / layer

Technology Feature:

Provide embedded ARRAY, embedded memory, embedded custom blocks, embedded IP, embedded special I/O……etc.
If customers request other devices(body), PGC can provide customize body devices for customers.
Pad size: 　80 x 578um² (width x length)
Pad opening: 　65 x 65um² (width x length)

Note:

Usable gates are estimated; the actual number of usable gates is design dependent.
I/O pads can be used as VDD/VSS pads.
There are four (4) dedicated VDD/VSS pads for each corner cell in the chip.