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DC ELECTRICAL CHARACTERISTICS

Process: 0.6 um
Operating Voltage: 4.5V～5.5V
VOL: 0.4v (MAXIMUM)
VOH: 2.4V (MINIMUM)
Usable Gate: 2,275～63,260
I/O Count: 48～240
Gate Delay: 0.21 ns
Gate Power@Freq.: 3.10 uW/Gate/MHZ
Output Drive: 2,4,8,12,16,24 mA
Temp Range - Commercial : 0°C ～+70°C
Pad size: 　100.8 x 480um² (width x length)
Pad window: 　83 x 83um² (width x length)

Device Name	Total I/O Pads	Max. I/O	Total Gate	DLM Usable Gate	TLM Usable Gate	Remark
TGT500006 TGT500012 TGT500017 TGT500027 TGT500038 TGT500056 TGT500069 TGT500092 TGT500119 TGT500158	64 84 96 116 136 160 176 200 224 256	48 68 80 100 120 144 160 184 208 240	5688 12084 16740 26520 38950 56316 69850 92564 119188 158530	2275 4833 6696 10608 13632 22526 24447 32397 41715 55485	4833 6696 10608 13632 22526 24447 32397 41715 55485 63260	Available Available Available Available Available Available Available

Engineer Sample lead time: 3 ~ 4 weeks

Mass Production lead time: 4 ~ 5 weeks

SUPER HOT RUN lead time : 2 ~ 3 weeks

Provide Gate Array Design Kit and Library

Above Estimated Schedule is based on 1P2M

Normal lead time: 2 ~ 3 days / layer

0.6um GATE ARRAY SERIES TSMC FAB
TGT550 Products

5" MASK 6" WAFER, Linear I/O