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Device	Supply Voltage	Total I/O Pads	Max I/O	TLM Usable Gate	QLM Usable Gate	Remark
HDA10100 HDA10120 HDA10144 HDA10160 HDA10184 HDA10208 HDA10240 HDA10316 HDA10468 HDA11152 HDA11208	3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V/5V 3.3V/5V	116 136 160 176 200 224 256 316 468 152 208	100 120 144 160 184 208 240 332 484 113 166	21953 28885 43415 54138 74537 96983 131733 277100 626670 100000 150000	25216 32736 49204 62263 84475 109914 149297 314047 710226 112000 170000	Available Available Available Available

Engineer Sample lead time: 3 ~ 4 weeks

Mass Production lead time: 4 ~ 5 weeks

SUPER HOT RUN lead time : 2 ~ 3 weeks

Provide Gate Array Design Kit and Library

Above Estimated Schedule is based on 1P2M

Normal lead time: 2 ~ 3 days / layer

Technology Feature:

Metal memory compiler (single-port RAM, dual-port RAM and ROM).
Provide embedded ARRAY, embedded memory, embedded custom blocks, embedded IP, embedded special I/O……etc.
If customers request other devices(body), PGC can provide customize body devices for customers.(HIGH PIN COUNT BODY DEVICES)
Pad size: 　62.5 x 671.55um² (width x length)
Pad opening: 　86 x 86um² (width x length)

Note:

Usable gates are estimated; the actual number of usable gates is design dependent.
I/O pads can be used as VDD/VSS pads.
There are four (4) dedicated VDD/VSS pads for each corner cell in the chip.

HIGH PIN COUNT BODY DEVICES

Device	1P3M Usable Gates (1)	1P4M Usable Gates (1)	Total I/O Pads	Max I/O
HDA10316 HDA10384 HDA10468 HDA10596 HDA10720 HDA10916 HDA101030 HDA101116	277100 416928 626670 1030605 1518485 2478506 3157524 3698323	314047 472518 710226 1168019 1720949 2808974 3578527 4191432	332 400 484 612 736 932 1048 1132	316 384 468 596 702 916 1032 1116

Note: Usable gates are estimated; the actual number of usable gates is design dependent.