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0.18um Process

Vendor P/N	Process	Description	Area (Mil^2)	IP Status	Datasheet
HD-SP-SRAM	0.18um 1P4M Logic Salicide	High Density Single Port Sync. SRAM	By Case	Memory Compiler
Sync-TP-SRAM	0.18um 1P4M Logic Salicide	Two Port Sync. SRAM	By Case	Memory Compiler
Sync-DP-SRAM	0.18um 1P4M Logic Salicide	Dual Port Sync. SRAM	By Case	Memory Compiler	Contact Us
HS-Sync-SROM	0.18um 1P4M Logic Salicide	High Speed Single Port Sync. ROM	By Case	Memory Compiler

0.25um Process

Vendor P/N	Process	Description	Area (Mil^2)	IP Status	Datasheet
SSC-T25	TSMC 0.25um generic	Synchronous Single-Port SRAM compiler	Cell size: 7.56 mil^2	Memory Compiler	Contact Us
HD-Single Port-SSRAM	0.25um 1P4M Logic Salicide	High Density Single Port Sync. SRAM	By Case	Memory Compiler	Contact Us
HD-Dual Port-SSRAM	0.25um 1P4M Logic Salicide	High Density Dual Port Sync. SRAM	By Case	Memory Compiler	Contact Us
HD-Single Port-ASRAM	0.25um 1P4M Logic Salicide	High Density Single Port Async. SRAM	By Case	Memory Compiler	Contact Us
HD-Dual Port-ASRAM	0.25um 1P4M Logic Salicide	High Density Dual Port Async. SRAM	By Case	Memory Compiler	Contact Us
RF-Sync-TP-SRAM	0.25um 1P4M Logic Salicide	Register File Two Port Sync. SRAM	By Case	Memory Compiler
RF-Sync-SP-SRAM	0.25um 1P4M Logic Salicide	Register File Single Port Sync. SRAM	By Case	Memory Compiler

0.35um Process

Vendor P/N

Process

Description

Area

(Mil^2)

IP Status

Datasheet

AROM32M

0.35um Flat-Cell

32M bit Mask ROM (4M*8/2M*16)

　

Production

Status	Description
Pre-Silicon	Design architecture completed based on simulation results.
Verification	Verified functionality in TSMC silicon.
Production	Production proven in at least one TSMC customer design.
License Type	Description
★	TSMC Specialized License Method.
Time (days)	Description
X ( Y )	X means PGC’s effort and Y means IP Vendor’s effort.

HIGH DENSITY MEMORY

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