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SOC DESIGN TURNKEY SERVICE

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MPW Turnkey Service Flow

MPW Turnkey Service Cycle Time

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ASIC Product Turnkey Service

ASIC Product Turnkey Service

SOC/ASIC Turnkey Capability

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Reliability Test

Failure Analysis

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LAYOUT Design Service

Layout Design Service Overview	Electromigration(Mars-rail)
Service Items	HPO-Antenna routing
Brief Layout Flow	Metal Layer & Via
Clock Tree Synthesis	Well Over Threshold
Clock Tree Synthesis Planning	Crosstalk Impaction on Circuits
Scan Chain Reordering	Crosstalk Avoidance Routing
Voltage(IR) Drop(Mars-rail)	LVS / DRC / ERC
Electromigration

SOC-IP

Cell & Memory Compiler IP

SOC / ASIC Design Turnkey Service

SOC Design Turnkey Service	Fault Simulation / Coverage Service Flow
SOC RTL Hand-off Flow(SOC RTL-QA)	Memory BIST Service Flow
SOC RTL-QA Analysis Flow Overview	SOC Low Power Service Flow
SOC Design Platform Service (RTLQA, STA, DFT and Low Power)	FIB Overview
SOC Design Platform Service Flow (Between PGC and Customer)	FIB Flow
Pre-Layout Sign-off Flow	ASIC Design Turnkey Service Memo
Pre-Layout Sign-off Flow	ASIC Design Turnkey Service Memo
Post-Layout Sign-off Flow	PGC ASIC Design Turnkey Service Process Schedule
SOC DFT and ATPG Service Flow	Mass Production Control Flow
Boundary Scan Service Flow	Package Offerings

Gate Array Design Turnkey Service

0.35um HDA10000

G/A Design Sign-off Flow

FPGA->Gate Array conversion

FPGA Converting and Verifying Flow