Untitled Document

IP / LIBRARY PORTFOLIO

HOME

MPW Shuttle Bus Service

MPW Service Programs

MPW Turnkey Service Flow

MPW Turnkey Service Cycle Time

MPW Shuttle Bus Schedule

Customer Request Form

SOC / ASIC Request Form

Gate Array Request Form

MPW Request Form

Layout Service Request Form

COT Request Form

ASIC Product Turnkey Service

ASIC Product Turnkey Service

SOC/ASIC Turnkey Capability

SOC/ASIC Turnkey Equipment

Turnkey Background

Reliability Test

Failure Analysis

Package Offerings

Success Cases

SiP Design Turnkey Service

SyStem-in-Package (SiP)	SiP Design Platform Service
SiP Punch Type Offering	SiP versus SOC
SiP Package	SiP Design Information
SiP Package Size	SiP Punch Type Offering
SiP Sawing Type Offering	SiP Developing Time
SiP Developing Flow	SiP Developing Design Fee
SiP Developing Flow	SiP Developing Design Fee
Electrical Simulation	Thermal Simulation
MCM QFP Stacked Die	SiP Side by Side
SiP Stacked(1) BGA	SiP Stacked(2) BGA
Package Stacking Package	SiP RF Package

About PGC

Company Profile(1)

Company Profile(2)

Business Principles

Company Organization

PGC Market Position

Employment

鏈結104網站

SOC-IP

Cell & Memory Compiler IP

SOC / ASIC Design Turnkey Service

SOC Design Turnkey Service	Fault Simulation / Coverage Service Flow
SOC RTL Hand-off Flow(SOC RTL-QA)	Memory BIST Service Flow
SOC RTL-QA Analysis Flow Overview	SOC Low Power Service Flow
SOC Design Platform Service (RTLQA, STA, DFT and Low Power)	FIB Overview
SOC Design Platform Service Flow (Between PGC and Customer)	FIB Flow
Pre-Layout Sign-off Flow	ASIC Design Turnkey Service Memo
Pre-Layout Sign-off Flow	ASIC Design Turnkey Service Memo
Post-Layout Sign-off Flow	PGC ASIC Design Turnkey Service Process Schedule
SOC DFT and ATPG Service Flow	Mass Production Control Flow
Boundary Scan Service Flow	Package Offerings

Gate Array Design Turnkey Service

0.35um HDA10000

G/A Design Sign-off Flow

FPGA->Gate Array conversion

FPGA Converting and Verifying Flow