IP / SUCCESS STORY (Projects & IPs)
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Over 1000 successful SOC/ASIC design projects (1991 - 2011)
Success Cases
90nm
0.13um
0.18um
0.25um
0.35um
0.5um
0.6um
SiP Turnkey Design Service
SyStem-in-Package (SiP)
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SiP versus SOC
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Electrical Simulation
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MCM QFP Stacked Die
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SOC-IP
Coming Soon IP
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Special I/O
Gate Array
SOC / ASIC Turnkey Design Service
SOC Turnkey Design Service
Fault Simulation / Coverage Service Flow
SOC RTL Hand-off Flow(SOC RTL-QA)
Memory BIST Service Flow
SOC RTL-QA Analysis Flow Overview
SOC Low Power Service Flow
SOC Design Platform Service (RTLQA, STA, DFT and Low Power)
FIB Overview
SOC Design Platform Service Flow (Between PGC and Customer)
FIB Flow
Pre-Layout Sign-off Flow
ASIC Turnkey Design Service Memo
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SOC DFT and ATPG Service Flow
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Boundary Scan Service Flow
Package Offerings
Gate Array Turnkey Design Service
0.35um HDA10000
0.5um HDA9000
0.6um HDA8000
0.6um TGT550
G/A Design Sign-off Flow
FPGA->Gate Array conversion
FPGA Converting and Verifying Flow
