CUSTOMER REQUEST (Gate Array)

CUSTOMER: APPLICATION: ¡@E-mail:
REQUEST BY: FAX: TEL:
PGC SALES: ¡@PM:                  Web:

DESIGN NAME:
1. DATA IN:RTL NETLIST FPGA¡@
2. PROCESS: 0.35um¡@¡@ 0.5um¡@¡@ 0.6um
¡@¡@¡@¡@¡@¡@W/ESD W/O ESD
3. G/A¡@¡@ EMB_G/A¡@¡@ P M
4. PACKAGE: ( * * )
¡@PB FREE TAPPING BGA/CSP (*)
¡@OPEN CLOSE TOOLNORMALPB FREE(W/Br)
¡@GREEN(Pb+Br Free) ¡@WAFER BASE DIE BASE
5. TOTAL PINS =
¡@ I/O PINS + POWER PINS
6. SUPPLY VOLTAGE(V):¡@CORE: ¡@I/O:
¡@ 5V TOLERANT¡@¡@ BOTH VDD=5V/3V
¡@ MIXED POWER VDD1=5V VDD2=3V
¡@ OTHERS
7. LOGIC GATES COUNT:
8. CLOCK FREQ.(Mhz) DOMAIN
9. MAX. DRIVE(mA):
10. SYNC. RAM:
11. ASYNC. RAM:
12. TWO PORTS RAM:
13. DUAL PORTS RAM:
14. ROM:
15. IP CELLS:

16. OPTION SERVICE:
¡@RTL QA-( Code Purification Performance Power
¡@ Testability Code Coverage) Analysis FIB DFT
¡@ ATPG FAULT COVERAGE LOW POWER
¡@ MEMORY BIST RELIABILITY TEST
¡@ PLOT LAYOUT ¡@ SUPER HOT RUN
¡@ PROBE CARD TOOLING
¡@ FPGA-GATE ARRAY¡@ BOUNDARY SCAN(JTAG)
¡@ COMMERCIAL INDUSTRIAL¢J ~ ¢J

*TAPE OUT DATE ¡@¡@SAMPLE DATE
*FORECAST O'TY /MONTH¡@ /YEAR
*TARGET NRE/UNIT
¡@PRICE












TGT550 (0.6um GATE ARRAY)
V Device Usable Gates Max. I/O
(1P2M) (1P3M)
TGT500006 2275 4833 48
TGT500012 4833 6696 68
TGT500017 6696 10608 80
TGT500027 10608 13632 100
TGT500038 13632 22526 120
TGT500056 22526 24447 144
TGT500069 24447 32397 160
TGT500092 32397 41715 184
TGT500119 41715 55485 208
TGT500158 55485 63260 240

HDA9000 (0.5um GATE ARRAY)
V Device Usable Gates Max. I/O¡@
(1P2M) (1P3M)
HDA9080 7245 12075 80
HDA9100 11988 19980 100
HDA9120 15231 25385 120
HDA9144 22603 37672 144
HDA9160 28285 47143 160
HDA9208 49303 82172 208
HDA9240 66596 110995 240
HDA9280 91708 152847 280

HDA10000 (0.35um GATE ARRAY)
V Device Usable Gates Max. I/O¡@
(1P3M) (1P4M)
HDA10120 28885 32736 120
HDA10144 43415 49204 144
HDA10160 54138 62263 160
HDA10184 74537 84475 184
HDA10208 96983 109914 208
HDA10240 131733 149297 240
HDA10280 182841 207220 280

¡@* Engineer Sample lead time: 3 ~ 4 weeks
¡@* Mass Production lead time: 4 ~ 5 weeks
¡@* SUPER HOT RUN lead time: 2 ~ 3 weeks
¡@* Provide Gate Array Design Kit and Library
¡@* 0.35um, 0.5um with Metal Memory Compiler
CUSTOMER SUGGESTION, SPECIAL REQUEST/REMARKS: