¡@¡@¡@¡@¡@CUSTOMER REQUEST (Gate Array)

CUSTOMER: APPLICATION: ¡@E-mail:
REQUEST BY: FAX: TEL:
PGC SALES:                  Web:


DESIGN NAME:
1. DATA IN:RTL NETLIST FPGA¡@
2. PROCESS: 0.13um 0.18um 0.35um 0.5um 0.6um     
¡@¡@¡@¡@¡@¡@W/ESD W/O ESD
3. G/A¡@¡@ EMB_G/A¡@¡@ P M
4. PACKAGE: ( * * )
¡@PB FREE TAPPING BGA/CSP (*)
¡@OPEN CLOSE TOOLNORMALPB FREE(W/Br)
¡@GREEN(Pb+Br Free) ¡@WAFER BASE DIE BASE
5. TOTAL PINS =
¡@ I/O PINS + POWER PINS
6. SUPPLY VOLTAGE(V):¡@CORE: ¡@I/O:
¡@ 5V TOLERANT¡@¡@ BOTH VDD=5V/3V
¡@ MIXED POWER VDD1=5V VDD2=3V
¡@ OTHERS
7. LOGIC GATES COUNT:
8. CLOCK FREQ.(Mhz) DOMAIN
9. MAX. DRIVE(mA):
10. SYNC. RAM:
11. ASYNC. RAM:
12. TWO PORTS RAM:
13. DUAL PORTS RAM:
14. ROM:
15. IP CELLS:

16. OPTION SERVICE:
¡@RTL QA-( Code Purification Performance Power
¡@ Testability Code Coverage) Analysis FIB DFT
¡@ ATPG FAULT COVERAGE LOW POWER
¡@ MEMORY BIST RELIABILITY TEST
¡@ PLOT LAYOUT ¡@ SUPER HOT RUN
¡@ PROBE CARD TOOLING
¡@ FPGA-GATE ARRAY¡@ BOUNDARY SCAN(JTAG)
¡@ COMMERCIAL INDUSTRIAL¢J ~ ¢J

*TAPE OUT DATE ¡@¡@SAMPLE DATE
*FORECAST O'TY /MONTH¡@ /YEAR
*TARGET NRE/UNIT
¡@PRICE












HDA8000 (0.6um GATE ARRAY)
V Device Usable Gates Max. I/O
(1P2M) (1P3M)
HDA8048 1318 2196 48
HDA8068 3229 5382 68
HDA8080 4762 7938 80
HDA8100 7938 13230 100
HDA8120 10246 17077 120
HDA8144 15301 25501 144
HDA8160 19225 32043 160
HDA8184 25962 43270 184
HDA8208 33770 56284 208
HDA8240 45590 75984 240
HDA8256 52126 86877 280

HDA9000 (0.5um GATE ARRAY)
V Device Usable Gates Max. I/O¡@
(1P2M) (1P3M)
HDA9080 4985 8308 68
HDA9080 7245 12075 80
HDA9100 11988 19980 100
HDA9120 15231 25385 120
HDA9144 22603 37672 144
HDA9160 28285 47143 160
HDA9208 49303 82172 208
HDA9240 66596 110995 240
HDA9280 91708 152847 280

HDA10000 (0.35um GATE ARRAY)
V Device Usable Gates Max. I/O¡@
(1P3M) (1P4M)
HDA10120 28885 32736 120
HDA10144 43415 49204 144
HDA10160 54138 62263 160
HDA10184 74537 84475 184
HDA10208 96983 109914 208
HDA10240 131733 149297 240
HDA10280 182841 207220 280

¡@* Engineer Sample lead time: 3 ~ 4 weeks
¡@* Mass Production lead time: 4 ~ 5 weeks
¡@* Provide Gate Array Design Kit and Library
¡@* 0.35um, 0.5um, 0.6um with Metal Memory Compiler

CUSTOMER SUGGESTION, SPECIAL REQUEST/REMARKS: