CUSTOMER REQUEST (SiP)

CUSTOMER: APPLICATION: E-mail:
REQUEST BY: FAX: TEL:
PGC SALES:                  Web:


DESIGN NAME: DATA IN:RTL NETLIST FPGA GDSII ECOMˇ@ˇ@OTHERS:
1.ˇ@PROCESS:16nm 28nm 28nm 40nm 65nm 90nm 0.11um 0.13um 0.18um 0.25um 0.35um 0.5um 0.6um P M
ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@EMB_FLASH
2.ˇ@CUSTOM FULLY:
ˇ@ˇ@
3.ˇ@CYBER SHUTTLE(MPW): SCHEDULE:
4.ˇ@STRUCTURED CELL ARTISANOTHERS
5.ˇ@PACKAGE:(**)mm Pb Free Tapping BGA/CSP (*)
ˇ@ˇ@OPEN CLOSE TOOLNORMALFLIP CHIPGREEN(Pb+Br Free)WAFER BASEDIE BASE
6.ˇ@TOTAL PINS = I/O PINS + POWER PINS
7.ˇ@SUPPLY VOLTAGE(V): CORE: Vˇ@I/O: Vˇ@ 5V TOLERANT
ˇ@ ˇ@ ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ MIXED POWER VDD1=5V VDD2=3Vˇ@OTHERS
8.ˇ@LOGIC GATES COUNT:
9.ˇ@CLOCK FREQ(Mhz) DOMAIN:
10.ˇ@ESTIMATED POWER DISSIPATION:W
11.ˇ@MEMORY IP:COMPILERTˇ@ˇ@HIGH DENSITYTˇ@ˇ@CUSTOM FULLYˇ@ˇ@EMB_BIST
ˇ@ˇ@SYNC. RAM:
ˇ@ˇ@ASYNC. RAM:
ˇ@ˇ@TWO PORTS RAM:
ˇ@ˇ@DUAL PORTS RAM:
ˇ@ˇ@ROM IP: DIFFUSION METAL ROM CONTACT
12.ˇ@FLASH IP:
13.ˇ@IP:
14.ˇ@CPUˇ@8 BITˇ@16 BITˇ@32BIT ˇ@
ˇ@ˇ@ˇ@OTHERS
15.ˇ@DSPˇ@ˇ@ARMˇ@ˇ@MIPSˇ@ˇ@OTHERS
16.ˇ@SOFTCORE IP:
ˇ@ˇ@USB(2.01.1) UDCHUBHOST
17.ˇ@MIXED MODE IP:PLL ˇ@ A/D D/A
18.ˇ@SPECIAL I/O IP:PCIe Gen2/Gen3 ˇ@ LVDS ˇ@ USB(2.03.0) ˇ@ I2C
ˇ@ˇ@DDR2/DDR3ˇ@ˇ@OTHERS
19.ˇ@TURNKEY TESTING: 1MHZ TEST PATTERNˇ@ˇ@10 MHZ TEST PATTERNˇ@ˇ@REAL TIME
ˇ@ˇ@BY OTHERSˇ@ˇ@COMMERCIALˇ@ˇ@INDUSTRIAL˘J ~ ˘J
20.ˇ@OPTION SERVICE:
ˇ@ˇ@RTL QA-(
Code Purification Performance Power Testability Code Covertage) Analysis
ˇ@ˇ@DFT ATPG FAULT COVERAGE LOW POWER MEMORY BIST RELIABILITY TEST
ˇ@ˇ@FIB SUPER HOT RUN PLOT LAYOUT PROBE CARD TOOLING
ˇ@ˇ@BOUNDARY SCAN(JTAG) SPLIT RUNˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@ˇ@OTHERS
21.ˇ@CUSTOMER SCHEDULE AND INFORMATION
ˇ@ˇ@TAPE OUT E/SQTY PCSˇ@PILOT RUN M/P
ˇ@ˇ@FORECAST Q'TY/MONTH,/YEAR
ˇ@ˇ@TARGET NRE/UNIT PRICE
ˇ@ˇ@TARGET CHIP SIZE MIL2 = mm2

SPECIAL REQUEST/REMARKS: