EMB_FLASH Design Turnkey Service.
SoC IC APR service and consulting.
Hierarchical Multi-million on gate APR and gate level floorplan.
Timing Driven/Power Driven/CTS(Clock Tree Synthesis) APR.
Signal integrity
(antenna/cross talk/voltage drop/electron-migration)
violation analysis and removal.
SOC integration.
LVS/DRC/ERC physical verification.
Scan chain re-ordering service
FIB service and consulting
Advanced 3D RC extraction(Gate Level and Transistor Level)
SDF generate and skew report(Utima/MDC)
Tape out
Service
ECO(Engineering Change Order) service
LAYOUT DESIGN SERVICE ITEMS
MPW Shuttle Bus Service
MPW Overview
MPW Service Programs
MPW Turnkey Service Flow
MPW Turnkey Service Cycle Time
Benefits
Success Cases
MPW Shuttle Bus Schedule
Customer Request Form
SOC / ASIC Request Form
Gate Array Request Form
MPW Request Form
Layout Service Request Form
COT Request Form
ASIC Product Turnkey Service
ASIC Product Turnkey Service
SOC/ASIC Turnkey Capability
SOC/ASIC Turnkey Equipment
Turnkey Background
Reliability Test
Failure Analysis
Package Offerings
Success Cases
90nm
0.13um
0.18um
0.25um
0.35um
0.5um
0.6um
About PGC
Company Profile(1)
Company Profile(2)
Business Principles
Company Organization
Sales Revenue
Roadmap
Location
PGC Market Position
Why PGC
Employment
人力資源
公司簡介
公司產品
鏈結104網站
LAYOUT Design Service
Layout Design Service Overview
Electromigration(Mars-rail)
Service Items
HPO-Antenna routing
Brief Layout Flow
Metal Layer & Via
Clock Tree Synthesis
Well Over Threshold
Clock Tree Synthesis Planning
Crosstalk Impaction on Circuits
Scan Chain Reordering
Crosstalk Avoidance Routing
Voltage(IR) Drop(Mars-rail)
LVS / DRC / ERC
Electromigration
SOC-IP
Coming Soon IP
Digital IP
Mixed Signal
Emb-Memory IP
Cell & Memory Compiler IP
Flash IP
Special I/O
Gate Array
SOC / ASIC Design Turnkey Service
SOC Design Turnkey Service
Fault Simulation / Coverage Service Flow
SOC RTL Hand-off Flow(SOC RTL-QA)
Memory BIST Service Flow
SOC RTL-QA Analysis Flow Overview
SOC Low Power Service Flow
SOC Design Platform Service (RTLQA, STA, DFT and Low Power)
FIB Overview
SOC Design Platform Service Flow (Between PGC and Customer)
FIB Flow
Pre-Layout Sign-off Flow
ASIC Design Turnkey Service Memo
Post-Layout Sign-off Flow
PGC ASIC Design Turnkey Service Process Schedule
SOC DFT and ATPG Service Flow
Mass Production Control Flow
Boundary Scan Service Flow
Package Offerings
Gate Array Design Turnkey Service
0.35um HDA10000
0.5um HDA9000
0.6um HDA8000
0.6um TGT550
G/A Design Sign-off Flow
FPGA->Gate Array conversion
FPGA Converting and Verifying Flow
