SUCCESS CASES
Process
Application
Technology
IP
0.18um IT Peripherals DC SCAN, Memory BIST PLL, DAC, eFlash, N9 CPU, USB1.1
0.18um Human body communication Low power solution, DFT, BIST H8S, FSK, Flash, regulator
0.18um VOIP Gate count : 150k
Frequency : 100M
ZSP400 , PLL , OSC , VCO , Voice CODEC
0.18um ADSL¥æ´«¾÷«áºÝ Gate count : 1.2 million
Frequency : 200M
ARM926EJ , PLL
0.18um Auto CE DFT, ATPG and BIST design Virage high density memory
Short I/O
ARM946E*2, ETM9
0.18um WLAN 1.2M gates ¡@¡@Freq:80MHZ
RTL to GDSII (fulfilled 50% ahead of customer's schedule)
Embedded PLL (input range 3.2MHZ ~ 150MHZ , output range 50MHZ ~ 500MHZ)
0.18um Computer Network 400K gates ¡@¡@Freq:125MHZ Embedded PLL, 338 memory instances
0.18um Lcd Controller 720K gates ¡@¡@Freq:133MHZ
Hierarchical Place and Route
ATPG, BIST design
Embedded PLL X 2
0.18um Graphic Controller 1.6 Million gates ¡@¡@Freq:80MHZ
Hierarchical Place and Route
DFT, ATPG and BIST design¡@
Cross-Talk,Vlotage Drop Analysis and removal
Scan-chain re-ordering
PLL
Memory
0.18um Wireless lan 1.3 Million gates¡@Freq:80MHZ
DFT, ATPG and BIST design
Cross-Talk,Vlotage Drop Analysis and removal
Scan-chain re-ordering
Embedded PLL ,High Density Sync-Ram
0.18um SDH DFT, ATPG and BIST design
Hierarchial layout
66MHZ¡@1 million gates
PLL
Memory
0.18um Game Controller DFT,ATPG,BIST design
70K gates , 50MHZ
Embedded RISC 8051 CPU
0.18um Base Station DFT, ATPG and BIST design
Two million Gates, 133MHz
PLL
173 Memory instances

 

 

 

 

 

 

 

 

Over 1000 successful SoC/ASIC projects (1991 - 2018)