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@TSMC 0.18um 1P6M Generic Process

1.2M gates     Freq: 80MHZ

RTL to GDSII (fulfilled 50% ahead of customer's schedule)

Embedded PLL (input range 3.2MHZ ~ 150MHZ , output range 50MHZ ~ 500MHZ)

Chip size: 189 mil x 189 mil

Application: WLAN

Customer: Japan

Over 900 successful SOC/ASIC design projects (1991 - 2008)