SUCCESS CASES
Over 1000 successful SOC/ASIC projects (1991 - 2017)

Process: 65nm 1P7M LP

Chip size : 4.6mm X 4.6mm

>3M Gates, 800MHz

Hierarchical layout, AC/DC SCAN, Memory BIST, JTAG1149.1

IP : PLL, DAC, N12 CPU, DDR2, USB2.0, USB3.0, HDMI

Application : 3C