SUCCESS CASES
Over 1000 successful SoC/ASIC projects (1991 - 2018)
Process
Application
Technology
IP
65nm GPS 7M Gates
Low power solution
DFT, MBIST
PLL
Memory
65nm 3C 3M Gates, 800MHz
Hierarchical layout
AC/DC SCAN, Memory BIST
JTAG1149.1
PLL, DAC, N12 CPU, DDR2
USB2.0, USB3.0, HDMI
65nm 3C 5M Gates, 800MHz
Hierarchical layout, AC/DC SCAN
Memory BIST, JTAG1149.1
PLL, DAC, LVDS, N12 CPU, DDR2, USB2.0, USB3.0, PCIe
65nm 3C 23M Gates, 500Mhz
Low power solution, DC/AC SCAN, MBIST
PCIe, LVDS, DDR3
65nm Network 12M Gates, 800MHz
Hierarchical layout, 9/12 track mixed core
PLL, DAC, ADC, LVDS, ARM9
65nm Wireless 4M Gates, 440MHz
Low power solution
Wireless analog, LVDS
65nm Ethernet 1M Gates, 125MHz
Low power solution, DFT
MV design for Single voltage internal power down (SVIPD)
UPF for R2GDSII power intent implementation/verification
Clock gating for dynamic power saving
Power gating for leakage power saving
Multi-Vt design for leakage power saving
Ethernet analog
65nm 32bits CPU 420K Gates, 595MHz
Low power solution, DFT, BIST
N1233_30S3L, PLL
110 Memories
65nm Wireless LAN 10M Gates, 160MHz
Low power solution, DFT, BIST
ADC*3, DAC*3, PLL*1
ARM946E-S, PCI core
110 Memories
65nm 3C RISC core
MTCMOS and Multi Voltage Low power solution
PCIe, LVDS, DDR3
65nm Ethernet 2M Gates, 300MHz
Low power solution, DFT
Ethernet analog