SUCCESS CASES
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Over 950 successful SOC/ASIC design projects (1991 - 2010)
Success Cases
90nm
0.13um
0.18um
0.25um
0.35um
0.5um
0.6um
SiP Turnkey Design Service
SyStem-in-Package (SiP)
SiP Design Platform Service
SiP Punch Type Offering
SiP versus SOC
SiP Package
SiP Design Information
SiP Package Size
SiP Punch Type Offering
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SiP Developing Flow
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Electrical Simulation
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MCM QFP Stacked Die
SiP Side by Side
SiP Stacked(1) BGA
SiP Stacked(2) BGA
Package Stacking Package
SiP RF Package
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SOC-IP
Coming Soon IP
Digital IP
Mixed Signal
Emb-Memory IP
Cell & Memory Compiler IP
Flash IP
Special I/O
Gate Array
SOC / ASIC Turnkey Design Service
SOC Turnkey Design Service
Fault Simulation / Coverage Service Flow
SOC RTL Hand-off Flow(SOC RTL-QA)
Memory BIST Service Flow
SOC RTL-QA Analysis Flow Overview
SOC Low Power Service Flow
SOC Design Platform Service (RTLQA, STA, DFT and Low Power)
FIB Overview
SOC Design Platform Service Flow (Between PGC and Customer)
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Pre-Layout Sign-off Flow
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SOC DFT and ATPG Service Flow
Mass Production Control Flow
Boundary Scan Service Flow
Package Offerings
Gate Array Turnkey Design Service
0.35um HDA10000
0.5um HDA9000
0.6um HDA8000
0.6um TGT550
G/A Design Sign-off Flow
FPGA->Gate Array conversion
FPGA Converting and Verifying Flow
