SUCCESS CASES
MPW Shuttle Bus Service
MPW Overview
MPW Service Programs
MPW Turnkey Service Flow
MPW Turnkey Service Cycle Time
Benefits
Success Cases
MPW Shuttle Bus Schedule
Customer Request Form
SOC / ASIC Request Form
Gate Array Request Form
MPW Request Form
Layout Service Request Form
COT Request Form
ASIC Product Turnkey Service
ASIC Product Turnkey Service
SOC/ASIC Turnkey Capability
SOC/ASIC Turnkey Equipment
Turnkey Background
Reliability Test
Failure Analysis
Package Offerings
Success Cases
90nm
0.13um
0.18um
0.25um
0.35um
0.5um
0.6um
SiP Turnkey Design Service
SyStem-in-Package (SiP)
SiP Design Platform Service
SiP Punch Type Offering
SiP versus SOC
SiP Package
SiP Design Information
SiP Package Size
SiP Punch Type Offering
SiP Sawing Type Offering
SiP Developing Time
SiP Developing Flow
SiP Developing Design Fee
Electrical Simulation
Thermal Simulation
MCM QFP Stacked Die
SiP Side by Side
SiP Stacked(1) BGA
SiP Stacked(2) BGA
Package Stacking Package
SiP RF Package
About PGC
Company Profile(1)
Company Profile(2)
Business Principles
Company Organization
Sales Revenue
Roadmap
Location
PGC Market Position
Why PGC
Employment
人力資源
公司簡介
公司產品
鏈結104網站
SOC-IP
Coming Soon IP
Digital IP
Mixed Signal
Emb-Memory IP
Cell & Memory Compiler IP
Flash IP
Special I/O
Gate Array
@TSMC 0.6um 1P2M 5V process
60K gates
Freq: 27MHZ
Application: CCTV
Over 1000 successful SOC/ASIC design projects (1991 - 2011)
SOC / ASIC Turnkey Design Service
SOC Turnkey Design Service
Fault Simulation / Coverage Service Flow
SOC RTL Hand-off Flow(SOC RTL-QA)
Memory BIST Service Flow
SOC RTL-QA Analysis Flow Overview
SOC Low Power Service Flow
SOC Design Platform Service (RTLQA, STA, DFT and Low Power)
FIB Overview
SOC Design Platform Service Flow (Between PGC and Customer)
FIB Flow
Pre-Layout Sign-off Flow
ASIC Turnkey Design Service Memo
Post-Layout Sign-off Flow
PGC ASIC Turnkey Design Service Process Schedule
SOC DFT and ATPG Service Flow
Mass Production Control Flow
Boundary Scan Service Flow
Package Offerings
Gate Array Turnkey Design Service
0.35um HDA10000
0.5um HDA9000
0.6um HDA8000
0.6um TGT550
G/A Design Sign-off Flow
FPGA->Gate Array conversion
FPGA Converting and Verifying Flow
