Success Story
成功案例
Roadmap ＆ Success Projects Overview
Roadmap ＆ Success
Projects Overview
Over 1000 successful ASIC design projects tape out at TSMC(1991 - 2024)
| Process | Application | Technology | IP |
|---|---|---|---|
| CoWoS | AI | Coworking with TSMC | |
| 3nm | AI | Coworking with Synopsys... | Synopsys IP OEM Program |
| 5nm | AI | Coworking with Synopsys... | Synopsys IP OEM Program |
| 6nm | AI | Coworking with Synopsys... | A76 core, Synopsys IP OEM Program |
| 7nm | Automotive | Coworking with Synopsys... | A76 core, Synopsys IP OEM Program |
| 7nm | AI | Coworking with Synopsys... | Synopsys IP OEM Program |
| 12nm | CPU | MPW, COT, DRC, LVS, Verification |
Memory PLL |
| 16nm | CPU | COT, DRC, Verification | CPU |
| 28nm | 5G | MPW, COT, DRC, LVS, Verification |
Memory PLL High Speed Interface I/O |
| 28nm | HPC | MLM, COT, DRC, LVS, Verification |
Memory PLL High Speed Interface I/O |
| 28nm | Image Processing |
533MHz Power Domain, Clock Domain, LVS, DRC, Verification |
MIPI-TX/RX ADC/DAC DDR I/O |
| 28nm | eMMC |
800MHz Power Domain, Clock Domain, LVS, DRC, Verification |
AIP, DDR I/O |
| 40nm | Wireless |
7M Gates, 440MHz Hierarchical layout, MV low power design |
Wireless Analog USB3.0 |
| 40nm | CPU |
600MHz Low Power Designt, Power Domain, Clock Domain LVS, DRC, Verification |
PLL Memory |
| 55nm | AIoT |
APR Layout, Power Domain, Clock Domain LVS, DRC, Verification |
Memory PLL Special I/O |
| 65nm | GPS |
7M Gates Low power solution DFT, MBIST |
PLL Memory |
| 65nm | 3C |
3M Gates, 800MHz Hierarchical layout AC/DC SCAN, Memory BIST JTAG1149.1 |
PLL, DAC, N12 CPU, DDR2 USB2.0, USB3.0, HDMI |
| 65nm | 3C |
5M Gates, 800MHz Hierarchical layout, AC/DC SCAN Memory BIST, JTAG1149.1 |
PLL, DAC, LVDS, N12 CPU, DDR2, USB2.0, USB3.0, PCIe |
| 65nm | 3C |
23M Gates, 500Mhz Low power solution, DC/AC SCAN, MBIST |
PCIe, LVDS, DDR3 |
| 90nm | Digital Camera |
3M Gates, 192MHz Low power solution, DFT, BIST |
ADC*1, DAC*3, PLL*3 ARM926EJ-S, USB*1, DDR2 58 Memories |
| 90nm | Industrial Controller |
Spec-in, ARM Platform Design 2M Gates, 533MHz Low power solution, DFT,MBIST |
ARM1176JSF, PCI Express PHY, USB2.0 OTG PHY AXI bus (PL301), DDRII controller, PCI controller PCI-E controller, USB 2.0 controller, Crypto Engine NAND Flash controller, Giga Ethernet MAC |
| 90nm | CPU |
Flip Chip 500Mhz |
LVDS, DDRII PHY 58 Memories |
| 90nm | Wireless LAN |
160MHz Low power solution, DFT, BIST |
ADC*3, DAC*3, PLL*1 ARM946E-S, PCI core 110 Memories |