Solution

SiP(System-in-Package) / 3D Package Turnkey Service

SiP Turnkey Design Solution

SiP Turnkey
Design Solution

SiP Package Type

SiP Package Type

• The System-in-Package (SiP) implements 2.5D & 3D technology in integrated modules with several chip packages arranged side by side or stacked, achieving functional systems or subsystems at the package level.
• SiP has primarily been used in mobile, HPC, automotive, and AI applications, … , etc. Based on the customer′s requirement, PGC could offer suitable SiP selections to ensure reducing costs and time to market.

• The figure above provides an overview of the SiP (System in Package) family. ASE primarily offers SiP packages that involve die combination and package combination using wire bonding, flip chip, and SMT interconnection technology.
• MPBGA
• 　　．KGD solution
• 　　．Multi functional components in package level
• 　　．High speed, high performance sub-system solution, efficiency in production
• Module
• 　　．Fully functional sub-system in LGA or BGA
• Stacked Die
• 　　．Major running type of SiP
• 　　．Improve electrical performance significantly
• Stacked Package
• 　　．KGD solution including PoP and PiP
• 　　．Each package is separately assembled and tested
• 　　．Improve package burn in test yield performance

Chip-Package- System Vertical Align

Chip-Package-
System Vertical Align

SiP Design

SiP Design

KGD Vendor Management

• Long term partnership with standalone memory suppliers.
• Logistic management and inventory control
• MOQ management
• Quality management
• Consign

SiP Design Platform Service

SiP Design
Platform Service

Electrical Simulation

Thermal Simulation

MCM QFP Stacked Die

SiP Side by Side

SiP Stacked BGA

SiP Success Story

Over 1000 successful ASIC design projects tape out at TSMC(1991 – 2024)

• Package: Flip Chip BGA 2601L
• Layer: 4+2+4 Layers
• Ball Diameter:0.6 (mm)
• Ball Pitch:1.0 (mm)
• U1:SoC
• U2:SoC
• Application: Super computer

• Package Type: STK LFBGA-100
• Layer: 4 layers
• Ball Pitch: 0.8 mm
• U1: ASIC
• U2: Flash
• Application: GPS

• Package Type: QFN-64L (Green)
• Pin Pitch: 0.5 mm
• U1: Flash
• U2: TTBD ASIC
• Application: GPS

• Package: SBS LFBGA 225L
• Layer: 4 Layers
• Ball Diameter:0.4mm
• Ball Pitch:0.8 mm
• U1:RF
• U2: Baseband ASIC
• Application: Wireless (Zigbee)

• Package: SBS LFBGA 112L
• Layer: 4 Layers
• Ball Diameter: 0.4(mm)
• Ball Pitch: 0.8(mm)
• U1: ASIC
• U2: SRAM 1Mbits(128K x 8bits)
• U3: Flash 4Mbits(512K x 8bits)
• Application: PLC

• Process: TSMC 90nm 1P10M Flip Chip (1150 balls)
• Frequency: 500Mhz
• IP : LVDS, DDRII PHY
• Application : CPU

• Process: TSMC 0.13um 1P8M Flip Chip
• IP : LVDS, USB2.0, PCIe, SATA2
• Application : I/O HUB

2.5D and 3D IC Packaging

3D Substrate Layout

3D Electrical Extraction